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Introduction to DSP

DSP processors: Review of DSP Processors

Although there are many DSP processors, they are mostly designed with the same few basic operations in mind: so they share the same set of basic characteristics. We can learn a lot by considering how each processor differs from its competitors, and so gaining an understanding of how to evaluate one processor against others for particular applications.

A simple processor design like the Lucent DSP32C shows the basic features of a DSP processor:

The DSP32C is unusual in having a true von Neuman architecture: rather than use multiple buses to allow multiple memory accesses, it handles up to four sequential memory accesses per cycle. The DMA controller handles serial I/O, independently in and out, using cycle stealing which does not disturb the DSP execution thread.

The simple DSP32C design uses the address registers to hold integer data: and there is no hardware integer multiplier: astonishingly, integers have to be converted to floating point format, then back again, for multiplication. We can excuse this lack of fast integer support by recalling that this was one of the first DSP processors, and it was designed specifically for floating point, not fixed point, operation: the address registers are for address calculations, with integer operations being only a bonus.

For a fixed point DSP, the address generation needs to be separated from the integer data registers: this may also be efficient for a floating point DSP if integer calculations are needed very often. Lucent's more modern fixed point DSP16A processor shows the separation of fixed point from address registers:

The DSP16A also shows a more conventional use of multiple internal buses (Harvard plus cache) to access two memory operands (plus an instruction) . A further arithmetic unit (shifter) has been added.

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